Senior ASIC Verification Engineer Sweden

Try running a new searchor browse our vacancies.

Or fill in the form below to receive job alerts.

Job Type	Temporary / Contract
Location	Stockholm
Area	Älta, Sweden Fisksätra, Sweden Märsta, Sweden Sjöberg, Sweden Södertälje, Sweden Stockholm, Sweden Sundbyberg, Sweden Täby, Sweden Vaxholm, SwedenÄltaSwedenStockholm
Sector	IT & Telecoms - RF & Baseband Engineer
Currency	SEK
Start Date
Job Ref	1011128
Job Views	11

Description: For our client we are looking for a Senior ASIC Verification Engineer.

Responsibilities & Tasks
• Define and implement UVM based test environments for IPs and subsystem.
• Develop, run and debug testcases.
• Usage of uVC´s
• Development of uVC´s (if needed)
• Usage of reference models (if needed)
• Constrained random testing
• Creation of Coverage matrix
• Writing Verification Report

Requirements
• Several years’ experience in verification using System Verilog and UVM
• Knowledge of Verilog/VHDL
• Knowledge of Object-Oriented Programming concepts
• Experience in developing test plans and directed/randomized test cases from scratch
• Experience in formal verification
• Experience with simulation verification tools (Mentor/Cadence)

Start: ASAP

Duration: 6 months, possibility of extension

Location: Kista

Keywords

Job TypeClear

Permanent Full Time

Temporary / Contract

Permanent Part Time

CurrencyClear

GBP

USD

EUR

SEK

Email address: